1. Field of the Invention
The invention relates to LSI complementary MOS field effect transistors (CMOS circuits) and somewhat more particularly to an improved method of producing adjacent tubs implanted with dopant ions in the manufacture of such circuits.
2. Prior Art
In known methods for manufacturing LSI complementary MOS field effect transistors circuits (CMOS circuits), multiple implantations according to various techniques, which are very involved, are employed for defining the different transistor threshold voltages.
Thus, L. C. Parillo et al, "Twin Tub CMOS-A Technology for VLSI Circuits", IEDM Technical Digest, pages 752-755 (1980) suggest a process of producing two n- or, respectively, p- tubs in a CMOS process by self-adjusting process steps with the use of only one mask. With a standard penetration depth x.sub.j =5.mu.m (n- and p- tubs), the self-adjusting implantation of two tubs leads to a high spatial overlap at the implantation edges and to a charge-wise compensation of the n- or p- implanted regions. A negative consequence of this is that the threshold voltage of the field oxide transistor is reduced and current amplification of the parasitic npn and pnp bipolar transistors is increased. This leads to an increasing "latch-up" susceptibility (which is the trigger probability of a parasitic thyristor). A substantial reduction of the thick oxide threshold voltage as well as "latch-up", lead to an outage of the particular component.
Another prior art technique which peforms both the two tub production as well as the channel and field implantation with the use of separate masks is suggested by Y. Sakai et al, "High Packing Density, High Speed CMOS (Hi-CMOS) Device Technology", Japanese Journal of Applied Physics, Vol. 18, Supplement 18-1, pages 73-78 (1978). A disadvantage of this technique is that the CMOS manufacturing process, already critical in terms of yield, is further burdened by a plurality of required masking steps.